The trend toward higher and higher density packaging means that chipmakers are being pressed to use the 3rd dimension to provide even higher density for their chip packages. There are a number of different ways to design 3D chip packages. For stacked packages, the placement accuracy of chip layers becomes more and more important as the number of layers increases. The co-planarity of the layers is also an extremely important issue.
3D considerations are also crucial to assembly of MEMS devices, as well as other advanced 3D structures, such as VCSEL arrays and smart pixel arrays. In all cases, 3D packaging requires unparalleled accuracy in the x-, y- and z-directions.
SET's Flip Chip and Die Bonders provide this accuracy, with post-bond accuracy down to 0.5 µm. SET Device Bonders also deliver high leveling accuracy which can be critical for stacked packages or 3D optoelectronic devices. Leveling accuracy as high as 10 µrad ensures that the 3D structure is correctly assembled and aligned. Any questions? info@set-sas.fr			Courtesy of IMEC

 Technology News

SET has developed a substrate chuck and a bond head with a localized confinement chamber which operates safely with reducing gases such as forming gas or formic acid vapor. This patented configuration has been successfully implemented on SET bonder models FC150 and FC300. Especially suited for 3D-IC and IR-FPA bonding applications, this machine function enables to remove or prevent oxide formation.
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 Conference Proceeding 

 Title: Die-to-Wafer bonding of thin dies using a 2-Step approach;
High Accuracy Placement, then Gang Bonding.*
* This material, presented at the IMAPS International Conference on Device Packaging
(March 8-11, 2010), is posted here with permission of IMAPS.

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 Technical Papers

The SET Technical Bulletin N°3, a compilation of technical articles featuring High Density 3D Interconnect with TSV applications, is now available! 
 Download your free copy!


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