Technical papers

Technical papers: Focus on bonding!

Results of the 2015 testbeam of 180 nm AMS High-Voltage CMOS sensor prototype

June 30, 2016Focus on bondingDPNC, University of Geneva, SwitzerlandDownload

Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC.

Evaluation of Sn-based Microbumping Technology for Hybrid IR Detectors, 10µm Pitch to 5µm Pitch

ECTC 2015Focus on bondingIMEC Leuven, Belgium SOFRADIR Veurey-Voroize, FranceDownload

Hybridization of Infrared detectors has relied on Indium balling for the last decades. Whereas this well-established process has proven its reliability through out the years, it becomes challenging to further decrease the balling pitch below 10µm, due to balling volume limitation.

Development done on Device Bonder to address 3D requirements in a Production Environment

Focus on bondingDownload

IWLPC 2014 focus on bonding SET, Saint-Jeoire, France

Key to the success of 3D integration will be the ability to accurately align and bond devices with aggressive feature sizes

Interconnect and bonding techniques for pixelated X-ray and gamma-ray detectors

7-12 September, 2014Focus on bondingUNIVERSITY OF SURREY, Guilford, Surrey, U.K.10th International Conference on Position Sensitive DetectorsDownload

In the last decade, the Detector Development at the Technology departmentof the Science and Technology Facilities Council (STFC), U.K., established a variety of fabrication and bonding techniques to build pixelated X-ray and y-ray detector systems such as the spectroscopic X-ray imaging detector HEXITEC.

Microbumping Technology for Hybrid IR detectors, 10µm pitch and beyond

EPTC 2014Focus on bondingIMEC Leuven, Belgium SOFRADIR Veurey-Voroize, FranceSingaporeDownload

In order to assess the feasability of a more mass-manufacturable process, IMEC has developed microbump technologies down to 10 µm pitch. The microbumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures.

Development done on Device Bonder to address 3D requirements in a production environment

IWLPC 2014Focus on bondingSET Saint-Jeoire, FranceSan Jose, CADownload

This paper will explore the above challenges in 3D HVMand will present solutions and trade-offs using a systemslevel approach

Die Attach Bonding using High-frequency Ultrasonic Energy for High-temperature application

June 2014Focus on bondingIME - Journal of Electronics materials (abstract)Download

Room-temperature die-attach bonding using ultrasonic energy was evaluatedon Cu/In and Cu/Sn-3Ag metal stacks.

Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications

June 2014Focus on bondingRTI InternationalDownload

The use of 3D integration technology in focal plane array imaging devices has been shown to increase imagingcapability while simultaneously decreasing device area and power consumption, as compared to analogous 2D designs.

High Density Interconnect Bonding of Heterogeneous Materials Using Non-Collapsible Microbumps at 10 μm Pitch

June 2014Focus on bondingRTI InternationalDownload

This paper reports on a successful demonstration of the use and reliability of CU/SN interconnection of heterogeneous semiconductor die.

Chip to wafer cooper direct bonding electrical characterization and thermal cycling

December 2013Focus on bondingCEA – LETI, MINATEC CampusDownload

Study of the recent achievements in cooper direct bonding technology with oxide/cooper mixed surface.

Micro-tube insertion into aluminum pads: Simulation and experimental validations

IMAPS 2013Focus on bondingCEA – LETI, MINATEC CampusDownload

Ultra-fine pitch flip-chip

9th International Conference and Exhibition on Device Packaging

This material is posted here with permission of IMAPS.

Aluminum to aluminum Bonding at Room Temperature

ECTC 2013Focus on bondingCEA – LETI, MINATEC CampusDownload

High density and very lowpitches face to face aluminum/aluminum cold bonding is feasable when using aluminum coated micro-tubes inserted into aluminum pads.

Chip to wafer direct bonding technologies for high density 3D integration

ECTC 2012Focus on bondingCEA – LETI, MINATEC, STMicroelectronics, SETDownload

Demonstration of chip to wafer assembly based on aligned Cu-Cu direct bonding.

A 10 μm Pitch Interconnection Technology using Micro Tube Insertion into Al-Cu for 3D Applications

ECTC 2011Focus on bondingCEA – LETI, MINATEC, LEM3 –CNRS/UPV-MDownload

Future 3-D applications require a very low pitch for interstrata vertical interconnection. The last ITRS assessment for vertical interconnection predicts a need for...

This material is posted here with permission of IEEE.

Low-Profile 3D Silicon-on-Silicon Multi-chip Assembly

ECTC 2011Focus on bondingIBM T.J. Watson Research CenterDownload

The focus of this paper is multi-chip 3D silicon-on-silicon assembly using low-profile lead-free (Sn-Cu) solder interconnects.

This material is posted here with permission of IEEE.

Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration

IMAPS 2010Focus on bondingRTI InternationalDownload

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermo-compression bonded dice....

This material is posted here with permission of Imaps.

Embedded active device packaging technology for real DDR2 memory chips

IWLPC 2010Focus on bondingIndustrial Technology Research Institute (ITRI)Download

As high-speed, high-density, and high-performance are the primary IC development targets, packaging becomes key technology...

Originally published in the IWLPC Proceedings

Fabrication and performance of InAs/GaSb-based superlattice LWIR detectors

SPIE Defense, Sensing & Security 2010Focus on bondingHRL LaboratoriesDownload

InAs/GaSb-based type II superlattices (T2SL) offer a manufacturable FPA technology with FPA size, scalability and cost advantages over HgCdTe.

Copyright 2010 SPIE

Ultrathin 3D ACA FlipChip-In-Flex Technology

ECTC 2010Focus on bondingBerlin Technical University, NB Technologies and Fraunhofer IZMDownload

Die thickness of common, high-volume chip stacks range between 50-100 µm while thinning industry aims towards ultrathin...

This material is posted here with permission of IEEE.

Three Chips Stacking with Low Volume Solder Using Single Re-Flow Process

ECTC 2010Focus on bondingInstitute of Microelectronics - A*STARDownload

A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed.

This material is posted here with permission of IEEE.

Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration

ECTC 2010Focus on bondingIMEC and the Katholieke Universiteit LeuvenDownload

A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed.

This material is posted here with permission of IEEE.

SET Technical Bulletin N°3

February 2010Focus on bondingCEA-Leti, IMEC, ITRI, IME-A*Star, RTI, etc...Download

It is a compilation of articles written by our clients. Each article provides unique insights into the exciting area of C2W and C2C bonding.

RF MEMS and flip-chip for space flight demonstrator

June 2009Focus on bondingThales Alenia SpaceDownload

The next generation of telecommunication satellites payloads will require higher performances and higher..

Electrical characterization of high count, 10 µm pitch, room-temperature vertical interconnections

Device Packaging 2009Focus on bondingCEA-LETIDownload

In order to increase the format of heterogeneous staring arrays to 2Kx2K pixels or even larger complexities, limited substrate size and cost...

This material is posted here with permission of Imaps.

New Reflow Soldering and Tip in Buried Box (TB2) Techniques For Ultrafine Pitch Megapixels Imaging Array

ECTC 2008Focus on bondingCEA-LETIDownload

Flip chip is a high-density and highly reliable interconnection technology which is mandatory for the fabrication of high end imaging arrays.

This material is posted here with permission of IEEE.

Technical papers: Focus on nanoimprinting!

NaPa "Library of Processes"

January 2010Focus on nanoimprintingNaPANILDownload

This FREE 152 pages book gives all directions needed to chose and apply an alternative nano-patterning technique: it is a must read for all!Access to NaPANIL's website:=> Please click on Direct Link to download it!

UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

November 2008Focus on nanoimprintingIISBDownload

Imprint specific process parameters like the residual layer thickness and the etch resistance of the UV polymers for the substrate etch process have to be optimized to introduce UV nanoimprint lithography (UV NIL) as a high-resolution, low-cost patterning technique... => Please click on Begin Search, type "schmitt" as person and "nanoimprint" as keyword.=> Then you will access to all latest papers!

UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

September 2008Focus on nanoimprintingIISBDownload

It's a poster

UV nanoimprinting lithography using nanostructured quartz molds with antisticking functionalization

February 2008Focus on nanoimprintingCNR-IMMDownload

In this paper, we report the results obtained by the application of the SET FC150 equipment for UV-NIL...

Conference proceeding

High Accuracy Flip-Chip Equipement

Conference proceedingDownload

Abstract
Consideration on the design of high precision Flip-chip bonder for mass production.

From / Presented by

Presented by Nicolas Raynaud from SET at European 3D Summit - Grenoble, France, 18-20 January 2016

Development done on Device Bonder to Address 3D Requirements in a Production Environment

Conference proceedingDownload

Abstract
Key to the success of 3D integration will be the ability to accurately align and bond devices with aggressive feature sizes

From / Presented by

Presented by Pascal Metzger from SET at IWLPC, San Jose, November 11-13, 2014

Flip-Chip Assembly FPA

Conference proceedingDownload

Abstract
Flip-Chip Assembly for Focal Plane Array

From / Presented by

Presented by Jean-Stéphane Mottet from SET at ORION - Moscow XXII International Conference Photoelectronics and Night Vision Devices, May 28th, 2014

Die-to-Die and Die-to-Wafer Bonding solution for High Density, Fine Pitch Micro-Bumped Die

Conference proceedingDownload

Abstract
Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a die-to-die and die-to-wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10µm micro-bumps at 20µm pitch.

From / Presented by

Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2012

Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme

Conference proceedingDownload

Abstract
This paper will review three major areas of process or equipment development surrounding the above problems, namely the issue of throughput enhancement by using a sacrificial adhesive to temporarily tack the dice before collective bonding, the issue of prior or in-situ removal and prevention of surface oxides at the bonding interface, and the issue of local environmental control to reduce particulates and other airborne contaminants. Each of these 3 will be explored with hardware solutions proposed, along with process results on test vehicles or functional devices.

From / Presented by

Presented by Keith Cooper from SET North America at IWLPC 2011

Chip-to-Wafer Technologies for High Density 3D Integration

Conference proceedingDownload

Abstract
CEA-Leti partnering with SET, STMicroelectronics, ALES and CNRS-CEMES on advanced Chip-to-Wafer technologies for 3D Integration in the frame of the PROCEED project, a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (<1µm) of chip-to-wafer structures made by direct metallic bonding.

From / Presented by

Penned by CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics and presented at MinaPad 2011

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

Conference proceedingDownload

Abstract
3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.

From / Presented by

Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2011

Flip-chip die bonding: an enabling technology for 3D integration

Conference proceeding

Abstract
3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together.

From / Presented by

Presented by Keith Cooper from SET North America at IWLPC 2010

Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding

Conference proceedingDownload

Abstract
25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm...

From / Presented by

Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2010

NIL technology

NPS300 Nano imPrinting Stepper

NIL technology

Low cost production solutions of nanostructures are in development that may be the driving forces of Semiconductor, MOEMS and optoelectronics technology tomorrow. In particular, Nanoimprint lithography (NIL) and its variations have been developed as a cost-effective alternative to high-resolution e-beam lithography to print sub-20 nm geometries.

Imprinting is based on the principle of mechanically pressing thin polymer film with a stamp containing the nanopattern, in a thermo-mechanical or UV curing process. The patterned polymer can act as a final device, e.g. lense for imaging sensors, micro fluidic chip, biomedical array etc. It can also be used as a high resolution mask for subsequent steps of the process.

Imprinting is a straightforward lithography technology. There are three basic process steps:

  • Align the stamp with the substrate which has been pre-coated with the imprinting material
  • Press the stamp into the imprinting material to transfer the pattern written on the stamp surface 
  • Separate the stamp from the imprinting material

We can describe three imprinting or embossing techniques: Hot Embossing Lithography (HEL) using thermal plastic material, UV-NIL using a liquid resist which is then cured with UV light after molding and Soft Lithography which transfers ink previously applied to a soft stamp onto a substrate using a stamping method.

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