Interconnexion 3D

Raccourcir les longueurs de connexion pour diminuer la résistance électrique, améliorer le temps de réponse ainsi que réduire la consommation d’énergie et les dimensions globales est un des principaux objectifs de l’intégration 3D.

Celle-ci permet l’assemblage de composants hétérogènes à haut rendement. Il existe de nombreuses solutions d’assemblage 3D comme :

  • Interposeur
  • Collage puce à puce direct
  • Interconnexion puce sur wafer

Le besoin en précision de placement dépend de l’application et de la méthode utilisée pour obtenir le signal en sortie du composant. L’industrie aujourd’hui se focalise sur les connexions par TSV (Via à Travers le Silicium) entre les couches de puces. L’optimisation du diamètre des TSV et de leur pas demande des précisions de placement encore plus grandes, non seulement selon X et Y, mais aussi en parallélisme entre puces.

Procédé d’assemblage

Une précision après-assemblage élevée et un bon parallélisme entre couches sont des paramètres cruciaux pour l’empilage 3D. Plusieurs procédés sont davantage dédiés à l’intégration 3D comme :

  • Refusion locale
  • Thermocompression
  • Assemblage par collage
  • Collage métallique direct
  • Etc…

Présentations aux conférences

TITLE

ABSTRACT

FROM / PRESENTED AT

Die-to-Die and Die-to-Wafer Bonding solution for High Density, Fine Pitch Micro-Bumped Die

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a die-to-die and die-to-wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10µm micro-bumps at 20µm pitch.

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2012

Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme

This paper will review three major areas of process or equipment development surrounding the above problems, namely the issue of throughput enhancement by using a sacrificial adhesive to temporarily tack the dice before collective bonding, the issue of prior or in-situ removal and prevention of surface oxides at the bonding interface, and the issue of local environmental control to reduce particulates and other airborne contaminants. Each of these 3 will be explored with hardware solutions proposed, along with process results on test vehicles or functional devices.

 Presented by Keith Cooper
from SET North America
at IWLPC 2011

Chip-to-Wafer Technologies for High Density 3D Integration

CEA-Leti partnering with SET, STMicroelectronics, ALES and CNRS-CEMES on advanced Chip-to-Wafer technologies for 3D Integration in the frame of the PROCEED project, a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (<1µm) of chip-to-wafer structures made by direct metallic bonding.

  penned by CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics and presented at MinaPad 2011

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2011

Flip-chip die bonding: an enabling technology for 3D integration

3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together.

 Presented by Keith Cooper
from 
SET North America
at IWLPC 2010

Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding

25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm...

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2010

 

Bulletin technique

Le Bulletin Technique n°3 de SET est une compilation d’articles techniques rédigés par quelques-uns de nos clients. Soigneusement organisé et présenté, chaque article propose un aperçu unique des domaines de soudage puce-à-puce et puce-sur-wafer.

 

 




A few titles:



 Study of 15μm Pitch Solder Microbumps for 3D-IC Integration; 
 
 A Fluxless Bonding Process using AuSn or Indium for a Miniaturized Hermetic Package;
 
 High Density Cu-Sn TLP Bonding for 3D Integration;


 Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps;


 An innovative die to wafer 3D integration scheme : Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling;

 

 

 Download the
SET Technical Bulletin N°3!