Conference Proceeding on 3D Packaging
Authors: Gilbert Lecarpentier*, Jean Stephane Mottet*, François Marion**
* SET S.A.S. (Smart Equipment Technology), 131 Impasse Barteudet, 74490 Saint Jeoire, France
** CEA-LETI Minatec - 17 rue des martyrs, 38054 Grenoble, France
Title: High accuracy placement, and in-situ reflow or thermo-compression bonding enabling high density and fine pitch in 3D-IC with chip-to-wafer bonding approach, illustrated by an application using micro-insertion.
With the advent of 3D-IC and the increased packaging density, the introduction of Through Silicon Via technology and the associated high accuracy placement and bonding challenges introduce new requirements to make chip to wafer population a reality. It becomes even more critical when chip sizes increase while the bumps dimensions or the TSV pitches decrease. The paper describes in-situ reflow and thermo-compression techniques compatible with interconnection metal-to-metal or with creation of inter metallic (i.e. Cu-Cu, CuSn). The thermo-compression will be illustrated by a technique of micro-insertion into indium for an imager application.
The 3D-IC Integration enables the continuation of Moore’s law . Wafer bonding techniques have been used for decades in various areas of microelectronics. The use of Wafer to Wafer bonding implies that chip dimension are identical for all layers and the yield decreased dramatically with the number of layers . Die-to-wafer bonding is an attractive and promising method, in which chips from one wafer are diced and then joined to another die or to a wafer . Thus, only good die are joined together and dissimilar technologies can be joined. With the introduction of high density Through Silicon Vias (TSV) with diameter down to 5 µm and below, together with the chip size increase, the Chip-to-Wafer Post Bond alignment accuracy becomes more stringent. Not only lateral positioning is important, but the parallelism of the die with respect to the wafer becomes a critical parameter.
2. Chip-to-Chip and Chip-to-Wafer Bonding
Compare to Wafer-to-Wafer bonding, Chip Stacking and Chip-to-Wafer (C2W) bonding approaches suffer of a potentially lower throughput since each die is placed individually. Bonding can be performed individually or, if the process allows, globally after placing all Chips. The lower Throughput is balanced by the benefit of bonding known good die to known good bonding site of the wafer, increasing the yield significantly.
Additionally, the Chip-to-Wafer (C2W) assembly method enables mixing heterogeneous technologies, side by side or stacked. Chip-to-Wafer bonding is also used for wafer reconstruction, chip resizing and connection redistribution to achieve 3D Die-stack of different technologies . Most of the bonding techniques used for die attach or flip-chip bonding (Fig.1) can be applied:
Thermo-compression including Cu-Cu bonding ,
Insertion bonding ,
Throughput is increased when using collective bonding techniques; two examples can illustrate this type of process:
a. Reflow soldering can be performed in neutral gas environment or vacuum:
At first step, chips are placed on the wafer using high throughput pick and place techniques,
At second step, collective reflow of the populated wafer insures soldering as well as final chip-to-wafer self-alignment in a dedicated process chamber (Fig.2).
b. Thermo compression bonding:
Collective bonding can be applied to thermo-compression using a tacking step,
Then a press with heating chucks completes the bond collectively.
Depending upon the interconnection density and the selected bonding technology, either pick-and-place machines or high accuracy die/device bonders are used for attachment of the die to the wafer or to the previous die.
For 3D-IC integration, the increased density of the Through Silicon Vias (TSV) requires submicron post bond accuracy and consequently Ultra High Accuracy Chip-to-Wafer (C2W) Bonder. The FC300, shown in figure 3, features 0.5 µm post bond accuracy using in situ thermo-compression; it has the potential of 0.25 µm when tacking at room temperature. The increase in density of bumps or TSV also impacts the parallelism requirement during placement and/or bonding sequences. The addition of a self leveling stage to an accurate die/flip-chip bonder, as shown on figure 4, enhances the bonding yield by improving the Chip-to-Wafer leveling without any loss in XY Accurate.
The positive action of the self leveling system has been demonstrated by a micro-insertion technique applied to infrared sensor at CEA/LETI. This technique has the advantages of requiring lower force , but need tighter control of the parallelism. It also enables soldering for ultra fine pitch of large devices .
Mixed “Pick & Place / Collective Bonding” processes technique can insure high throughput when decoupling operations. 3D-IC at wafer level using chip-to-wafer bonding method can guarantee high density packaging, thanks to the submicron post bonding accuracy of the assembly technology. Increased density requires higher placement accuracy and tighter control of the parallelism; yield improvement is obtained by using self leveling capability.
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