Conference Proceeding on 3D Packaging

Authors: Gilbert Lecarpentier*, Jean Stephane Mottet*, François Marion**
* SET S.A.S. (Smart Equipment Technology), 131 Impasse Barteudet, 74490 Saint Jeoire, France
** CEA-LETI Minatec - 17 rue des martyrs, 38054 Grenoble, France

Title: High accuracy placement, and in-situ reflow or thermo-compression bonding enabling high density and fine pitch in 3D-IC with chip-to-wafer bonding approach, illustrated by an application using micro-insertion.

 With the advent of 3D-IC and the increased packaging density, the introduction of Through Silicon Via technology and the associated high accuracy placement and bonding challenges introduce new requirements to make chip to wafer population a reality. It becomes even more critical when chip sizes increase while the bumps dimensions or the TSV pitches decrease. The paper describes in-situ reflow and thermo-compression techniques compatible with interconnection metal-to-metal or with creation of inter metallic (i.e. Cu-Cu, CuSn). The thermo-compression will be illustrated by a technique of micro-insertion into indium for an imager application.

 Download the entire presentation*. 
*This material, presented at the 2009 International Device Packaging Conference, is posted
here with permission of IMAPS.

1. Introduction



The 3D-IC Integration enables the continuation of Moore’s law [1]. Wafer bonding techniques have been used for decades in various areas of microelectronics. The use of Wafer to Wafer bonding implies that chip dimension are identical for all layers and the yield decreased dramatically with the number of layers [2].  Die-to-wafer bonding is an attractive and promising method, in which chips from one wafer are diced and then joined to another die or to a wafer [3]. Thus, only good die are joined together and dissimilar technologies can be joined. With the introduction of high density Through Silicon Vias (TSV) with diameter down to 5 µm and below, together with the chip size increase, the Chip-to-Wafer Post Bond alignment accuracy becomes more stringent. Not only lateral positioning is important, but the parallelism of the die with respect to the wafer becomes a critical parameter.





2. Chip-to-Chip and Chip-to-Wafer Bonding



Compare to Wafer-to-Wafer bonding, Chip Stacking and Chip-to-Wafer (C2W) bonding approaches suffer of a potentially lower throughput since each die is placed individually. Bonding can be performed individually or, if the process allows, globally after placing all Chips. The lower Throughput is balanced by the benefit of bonding known good die to known good bonding site of the wafer, increasing the yield significantly.




Additionally, the Chip-to-Wafer (C2W) assembly method enables mixing heterogeneous technologies, side by side or stacked. Chip-to-Wafer bonding is also used for wafer reconstruction, chip resizing and connection redistribution to achieve 3D Die-stack of different technologies [4]. Most of the bonding techniques used for die attach or flip-chip bonding (Fig.1) can be applied:




Throughput is increased when using collective bonding techniques; two examples can illustrate this type of process:


a. Reflow soldering can be performed in neutral gas environment or vacuum:
 At first step, chips are placed on the wafer using high throughput pick and place techniques,
 At second step, collective reflow of the populated wafer insures soldering as well as final chip-to-wafer self-alignment in a dedicated process chamber (Fig.2).




b. Thermo compression bonding:
 Collective bonding can be applied to thermo-compression using a tacking step,
 Then a press with heating chucks completes the bond collectively.

Depending upon the interconnection density and the selected bonding technology, either pick-and-place machines or high accuracy die/device bonders are used for attachment of the die to the wafer or to the previous die.





3. Conclusions

Mixed “Pick & Place / Collective Bonding” processes technique can insure high throughput when decoupling operations. 3D-IC at wafer level using chip-to-wafer bonding method can guarantee high density packaging, thanks to the submicron post bonding accuracy of the assembly technology. Increased density requires higher placement accuracy and tighter control of the parallelism; yield improvement is obtained by using self leveling capability.

4. References

[1] Future ICs Go Vertical, Philip Garrou, MCNC Research & Development Institute, Research Triangle Park, N.C. Semiconductor International 2/1/2005.
[2] Requirements for cost effective 3D integration, Pieters Philips, IMEC, 15th Annual International KGD Packaging & Test Workshop, 2008.
[3] Marion, Tissot “Collective flip chip technology for IRFPA”, Photonics China 96 SPIE Vol. 2894 1996.
[4] Ultra-Low-Profile 3-D Cube with Wafer-Level Packaging technique, Christian Val, 3D-Plus, IWLPC, San Jose, California, 2005.
[5] Direct Cu-Cu Thermo-Compression Bonding for 3D-Stacked IC Integration, Wouter Ruythooren, Serguei Stoukatch, Konstantina Lambrinou, Piet de Moor, Bart Swinnen; IMEC, Leuven, Belgium, IMAPS 2006, San Diego.
[6] Davoine, Fendler, Marion, “Low temperature fluxless F/C technology for fine pitch bonding”, proceedings of ECTC San Diego, 2006, p 24-28.
[7] Die-to-Wafer molecular bonding for optical interconnects and packaging, M. Kostrzewa, L. DiCioccio, J.M. Fedeli, J.C. Roussin, N. Kernevez; CEA-DRT-LETI, Grenoble, F; P.Regreny, Ecole Centrale de Lyon, LEOM, UMR CNRS, Ecully, F; EMPC 2005, Brugges, Belgium.
[8] C. Davoine, M. Fendler, F. Marion, “Low temperature F/C technology for fine pitch bonding”, Proc of ECTC San Diego, 2006, p 24-28.
[9] D. Saint-Patrice, F. Marion and all. New Reflow Soldering and Tip in Buried Box (TB2) Techniques For Ultrafine Pitch Megapixels Imaging Array Proceedings ECTC Orlando FL2008 pp 46-53.