3D互连

缩短连接长度以降低电阻,提高响应速度,以及减少功耗和整体尺寸,是3D集成的主要目标之一。

3D-IC 集成使得异构器件的高产组装成为可能。目前有多种3D封装解决方案,例如:

  • 接板,
  • 直接芯片对芯片接合或者是裸片对裸片接合,
  • 芯片对晶圆互连。

对定位精度的要求随应用情况以及从每个裸片中获取信号所使用的方法不同而变化。目前芯片层之间的硅通孔(TSV)互连是行业关注的焦点。TSV的直径和间距的优化正在使对位置精度(不仅是沿X轴和Y轴,而且也包括芯片之间的平行度)的要求变得更高。
 

接合工艺

接合后的高精度以及每一层之间良好的平行度是3D堆叠的关键参数。在SET的Flip-Chip Bonder上可以使用多种专用于3D集成的接合工艺,比如:

  • 原位回流焊,
  • 热压
  • 粘接
  • 直接金属键合

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会议文献

TITLE

ABSTRACT

FROM / PRESENTED AT

Die-to-Die and Die-to-Wafer Bonding solution for High Density, Fine Pitch Micro-Bumped Die

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a die-to-die and die-to-wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10µm micro-bumps at 20µm pitch.

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2012

Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme

This paper will review three major areas of process or equipment development surrounding the above problems, namely the issue of throughput enhancement by using a sacrificial adhesive to temporarily tack the dice before collective bonding, the issue of prior or in-situ removal and prevention of surface oxides at the bonding interface, and the issue of local environmental control to reduce particulates and other airborne contaminants. Each of these 3 will be explored with hardware solutions proposed, along with process results on test vehicles or functional devices.

 Presented by Keith Cooper
from SET North America
at IWLPC 2011

Chip-to-Wafer Technologies for High Density 3D Integration

CEA-Leti partnering with SET, STMicroelectronics, ALES and CNRS-CEMES on advanced Chip-to-Wafer technologies for 3D Integration in the frame of the PROCEED project, a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (<1µm) of chip-to-wafer structures made by direct metallic bonding.

  penned by CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics and presented at MinaPad 2011

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2011

Flip-chip die bonding: an enabling technology for 3D integration

3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together.

 Presented by Keith Cooper
from 
SET North America
at IWLPC 2010

Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding

25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm...

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2010

 

技术公告

SET技术公报n°3是我们的一些客户编写的技术文章的汇编。每篇文章的内容组织和呈现都很整洁简练,对裸片对裸片及裸片对晶圆接合这一令人兴奋的领域,它们提供了独特的见解。

 

 

 




A few titles:



 Study of 15μm Pitch Solder Microbumps for 3D-IC Integration; 
 
 A Fluxless Bonding Process using AuSn or Indium for a Miniaturized Hermetic Package;
 
 High Density Cu-Sn TLP Bonding for 3D Integration;


 Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps;


 An innovative die to wafer 3D integration scheme : Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling;

 

 

 Download the
SET Technical Bulletin N°3!