射频应用

虽然射频器件通常不需要高精度的接合,但是近期的一些应用已经表明,其需要更好地控制接合过程。

对于诸如先进卫星系统的某些RF应用来说,越来越期待高精度对准(芯片和基板之间的精度要在1微米之内)。RF器件采用的典型的金对金接合技术在高温条件下需要非常大的力,而这通常无法实现高精度。

即使是在高温和大力度的条件下,SET 的Flip Chip Bonder也能安全和轻松地处理脆性材料,同时,它还能增强对整个循环过程中力分布的控制,从而提高接合精度。通过高性能热压和调平能力,SET使高端射频连接成为现实,其准确度水平为射频应用设定了新的标准。
 

会议文献

TITLE

ABSTRACT

FROM / PRESENTED AT

Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme

This paper will review three major areas of process or equipment development surrounding the above problems, namely the issue of throughput enhancement by using a sacrificial adhesive to temporarily tack the dice before collective bonding, the issue of prior or in-situ removal and prevention of surface oxides at the bonding interface, and the issue of local environmental control to reduce particulates and other airborne contaminants. Each of these 3 will be explored with hardware solutions proposed, along with process results on test vehicles or functional devices.

 Presented by Keith Cooper
from SET North America
at IWLPC 2011

Chip-to-Wafer Technologies for High Density 3D Integration

CEA-Leti partnering with SET, STMicroelectronics, ALES and CNRS-CEMES on advanced Chip-to-Wafer technologies for 3D Integration in the frame of the PROCEED project, a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (<1µm) of chip-to-wafer structures made by direct metallic bonding.

  penned by CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics and presented at MinaPad 2011

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2011

Flip-chip die bonding: an enabling technology for 3D integration

3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together.

 Presented by Keith Cooper
from 
SET North America
at IWLPC 2010

Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding

25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm...

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2010

 

技术公告

SET技术公报n°3是我们的一些客户编写的技术文章的汇编。每篇文章的内容组织和呈现都很整洁简练,对裸片对裸片及裸片对晶圆接合这一令人兴奋的领域,它们提供了独特的见解。

 

 

 




A few titles:



 Study of 15μm Pitch Solder Microbumps for 3D-IC Integration; 
 
 A Fluxless Bonding Process using AuSn or Indium for a Miniaturized Hermetic Package;
 
 High Density Cu-Sn TLP Bonding for 3D Integration;


 Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps;


 An innovative die to wafer 3D integration scheme : Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling;

 

 

 Download the
SET Technical Bulletin N°3!