Direct Bonding

Direct Metallic Bonding is method used to assemble two components. Despite its main difficulty, the requirement of high level of cleanliness, several assets like low bonding force, room temperature process, short process time, make it as a serious candidate for advanced chip-to-wafer technologies applicable to 3D integration.

The 2-Year Minalogic project (Proceed) was supported by French FUI (Fond Interministériel Unique) with the objective of demonstrating high placement accuracy (< 1μm) of chip to wafer structures by direct metallic bonding. The project, led by SET, was developed through a partnership with:

  • CEA-Leti,
  • ST-Microelectronics
  • ALES

A special FC300 system, adapted to direct metallic bonding requirements for high level of cleanliness, has been developed and installed at CEA-Leti to explore chip-to-wafer structures by direct metallic bonding for 3D interconnect.


The PROCEED Minalogic project is a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (< 1 µm) of chip-to-wafer structures made by direct metallic bonding. Such structures are required for high performance 3D interconnexion circuits and enable a wide range of applications in microelectronics as well as in optoelectronics or MEMS.

Direct copper-to-copper bonding requires good planarity and excellent surface quality especially in terms of both particulate and metallic contamination. The low roughness of the copper pillars and pads as well as the topography between the copper and oxide areas are critical to obtain good bond strength at low force and room temperature.

The process, based on chip-to-wafer direct metallic bonding, is developed at CEA-Leti to overcome certain limitations in 3D integration. This technology consists of attaching chips on a substrate at low temperature and force, creating a bond of high mechanical and electrical integrity due to local metallic bonding.

ALES supplys technology to support the surface preparation while CEMES-CNRS characterizes the bond quality and analyzes changes to the copper metallurgy during the annealing step. STMicroelectronics is driving the application of this technology for the high density 3D integration.

Technology Benefits

This direct metal-to-metal bonding technology offers many advantages compare to conventional thermo-compression bonding.

The bonding process takes place at low force and room temperature, enabling higher accuracy bonding for high density interconnections by circumventing thermal expansion of differing materials. To ensure void-free bonding, the alignment and bonding steps must take place in a particle-free environment. It is accomplished by the use of special materials and careful management of the bonding environment to protect the wafer surface while it is fully populated with dice. 

A low-force bonding process is key to the high throughput required for widespread adoption of 3D IC Integration.

Technical Papers




Chip-to-Wafer Technologies for High Density 3D Integration

May 2011

  CEA Leti Minatec, ALES, STMicroelectronics, CNRS-CEMES, SET