MEMS封装

如今,所有的半导体制造技术都对材料、尺寸和加工参数进行了限制。这就为具有跨学科性质的MEMS系统器件设定了严格的设计界限。

对机械元件和辅助性电子元件进行微集成的能力,使得微机电系统(MEMS)成为了一项在众多领域得到应用的关键技术。人们对此产生了极大的兴趣。3-D MEMS器件的制造当然得益于半导体行业中所使用的相同的设备和标准化的工艺。

接合工艺

为了绕过这些限制,可以将传统工艺和新兴技术相结合使用来单独构建子元件。
然后,可以组装或混合这些元件,以制造更精密的器件。然而,针对每一个元件的传输、操纵、对准以及贴附,对这一方案提出了许多挑战。
SET FC150自动器件接合机展示出了处理精密器件(小于200微米)的卓越能力,它使用真空吸盘,并且其对准精度小于±1微米。
MEMS器件,比如自适应光学系统或高端喷墨打印机头,均已能够用SET的倒装焊机(Flip-Chip Bonder)实现完美封装。

会议文献

TITLE

ABSTRACT

FROM / PRESENTED AT

Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme

This paper will review three major areas of process or equipment development surrounding the above problems, namely the issue of throughput enhancement by using a sacrificial adhesive to temporarily tack the dice before collective bonding, the issue of prior or in-situ removal and prevention of surface oxides at the bonding interface, and the issue of local environmental control to reduce particulates and other airborne contaminants. Each of these 3 will be explored with hardware solutions proposed, along with process results on test vehicles or functional devices.

 Presented by Keith Cooper
from SET North America
at IWLPC 2011

Chip-to-Wafer Technologies for High Density 3D Integration

CEA-Leti partnering with SET, STMicroelectronics, ALES and CNRS-CEMES on advanced Chip-to-Wafer technologies for 3D Integration in the frame of the PROCEED project, a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (<1µm) of chip-to-wafer structures made by direct metallic bonding.

  penned by CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics and presented at MinaPad 2011

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 2011

Flip-chip die bonding: an enabling technology for 3D integration

3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together.

 Presented by Keith Cooper
from 
SET North America
at IWLPC 2010

Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding

25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm...

 Presented by Gilbert Lecarpentier from SET at Imaps Device Packaging 201

 

技术公告

SET技术公报n°3是我们的一些客户编写的技术文章的汇编。每篇文章的内容组织和呈现都很整洁简练,对裸片对裸片及裸片对晶圆接合这一令人兴奋的领域,它们提供了独特的见解。

 

 

 




A few titles:



 Study of 15μm Pitch Solder Microbumps for 3D-IC Integration; 
 
 A Fluxless Bonding Process using AuSn or Indium for a Miniaturized Hermetic Package;
 
 High Density Cu-Sn TLP Bonding for 3D Integration;


 Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps;


 An innovative die to wafer 3D integration scheme : Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling;

 

 

 Download the
SET Technical Bulletin N°3!